1. Field of the Invention
The present invention relates generally to a method of controlling an etching process for forming an epitaxial structure, and more specifically to a method of controlling an etching process for forming an epitaxial structure that adjusts the parameters of an etching process according to a thickness of a spacer to control the position of the formed epitaxial structure.
2. Description of the Prior Art
For decades, chip manufacturers have made metal-oxide-semiconductor (MOS) transistors faster by making them smaller. As the semiconductor processes advance to very deep sub micron era, such as the 65-nm node or beyond, how to increase the driving current for MOS transistors has become a critical issue. In order to improve devices performances, crystal strain technology has been developed. Crystal strain technology is becoming more and more attractive as a means for getting better performances in the field of MOS transistor fabrication. Putting a strain on a semiconductor crystal alters the speed at which charges move through that crystal. Strains make the CMOS transistors work better by enabling electrical charges, such as electrons, to pass more easily through the silicon lattice of the gate channel. In the known arts, attempts have been made to use a strained silicon layer that was grown epitaxially on a silicon substrate with a silicon germanium (SiGe) structure or a silicon carbide structure disposed in between. In this type of MOS transistor, a biaxial tensile strain occurs in the epitaxy silicon layer due to the silicon germanium structure or the silicon carbide structure having a larger or a smaller lattice constant than silicon, and, as a result, altering the band structure, thereby increasing the carrier mobility. This enhances the speed performances of the MOS transistors. Furthermore, the volume, the shape and the horizontal distance to gate of the epitaxial structure would also affect the electrical performances of the formed transistor.